Digital Arithmetic Projects

Fast Parallel Multiplier Design 

(Contact:  Mr. M.J. Liebelt, mike@eleceng.adelaide.edu.au)

The development of the single-chip multiplier has been one of the key innovations spurring the massive recent growth of graphics and DSP hardware. These chips (and CPUs to a lesser extent) benefit greatly from any improvement in speed or throughput/area that can be made to the multiplier design. Tree-based multiplier schemes are the fastest known, but significant difficulties occur in determining the optimal tree structure for a given problem. Our work looks to overcome these on two fronts – by improving the speed of an optimal tree-finding heuristic and by finding better algorithms for generating near-optimal reduction trees. There is also an opportunity for work designing matched final adder structures.

Support: The University of Adelaide

The Design of Arithmetic Systems using the Residue Number System

(Contact:  Dr. B.J. Phillips, phillips@eleceng.adelaide.edu.au)

The residue number system (RNS) has long been known as an efficient means of implementing multiplication, addition and subtraction; however, other basic arithmetic operations such as division, magnitude comparison and scaling are usually seen as too inefficient in RNS to make the system attractive for all but a very few specialized applications. Recent advances in RNS theory are beginning to change this view and RNS implementations of digital signal processing and cryptography are beginning to emerge. This project aims to advance the theory of RNS through investigation of the underlying arithmetic and also through implementation of systems employing RNS.

Support: The University of Adelaide

Arithmetic Data Value Speculation

(Contact:  Dr. B.J. Phillips, phillips@eleceng.adelaide.edu.au)

Modern computers frequently use guesswork. Rather than wait for an exact result they guess the outcome and race ahead, speculatively executing code. Guesswork of this kind is widely used to predict true or false conditions and data loaded from memory, but is not yet applied to results of arithmetic operations. However the quest for even faster computers is set to see data value speculation become an important technique. The design of small, fast arithmetic units to produce estimated results is a new and exciting avenue of research. This project will see a variety of these units built and tested. It will also explore new microprocessor architectures to take advantage of arithmetic speculation.

Support: The University of Adelaide

Design of High Performance, Compact, Low Power Arithmetic Systems Based on Threshold Logic

(Contact:  Dr. D. Abbott, dabbott@eleceng.adelaide.edu.au)

In recent years, there has been renewed interest in threshold logic, mainly as a result of the development of a number of successful implementations of CMOS threshold logic gates. Threshold logic enables the design of digital integrated circuits with a significant reduction in transistor count, area and power dissipation, and improved speed performance. In this project, we investigate the design of arithmetic circuits including parallel counters, adders and multipliers based in two high performance threshold logic gate implementations which we have developed.

Support: The University of Adelaide