Digital Microelectronic Projects

Multi-Channel Reconfigurable High Dynamic Range Digital Receivers

(Contact:  Dr. C.C. Lim, cclim@eleceng.adelaide.edu.au)

Wireless systems will increasingly require much higher levels of performance, in the form of abilities to receive and to distinguish signals from multiple sources that are physically close together and transmit on similar frequencies. In this project we develop a test system that will allow us to undertake research on new algorithms that will achieve these higher levels of performance. Our objective is to demonstrate dramatic improvements in the capacities of receivers for defence surveillance and future generation mobile phone systems. We have designed for CMOS fabrication a high-precision digital down converter (DDC) chip with internal bus widths and arithmetic to allow the exploitation of spatial dynamic range enhancement. Under development is a multi-channel reconfigurable high dynamic range digital receiver to be used in a remote and distributed environment. An immediate application is for improved multi-channel processing in LLISP ionosonde. The test system will be configured to analyse wideband vector signals for devising signal detection and separation algorithms in OFDM systems.

Support: Australian Research Council, Ebor Computing, Defence Science and Technology Organisation

High Speed Processor Architectures for Machine Learning Algorithms

(Contact:  Dr. C.C. Lim, cclim@eleceng.adelaide.edu.au)

Support vector machine (SVM) is a learning algorithm. Its major use has been for supervised classification. In order to obtain good generalisation in practical applications, an enormous number of examples for training are required. This places huge computational demand on conventional hardware. Since the formulation of SVM is inherently a dense matrix quadratic optimisation problem, we can extend our earlier work on high performance parallel matrix processors to devise parallel processing architectures and algorithms for running machine learning algorithms at computing rates that are orders of magnitude faster than is currently feasible. These architectures and algorithms are applicable to problems such as automatic channel classification in wideband communications systems, and feature recognition in radar images.

Support: Australian Research Council, Lucent Technologies, The University of Adelaide

Micro-Thread Optimisations

(Contact:  Mr. M.J. Liebelt, mike@eleceng.adelaide.edu.au)

This project is researching the viability of using micro-threads in a multi-threaded architecture to optimise processor performance. Due to a lack of parallelism, many of a processor’s functional units are not issued instructions in each cycle. Consequently, micro-threads can be executed without impeding normal program execution. Using these micro-threads to monitor and optimise processor activity can result in an increase in performance. Currently we are investigating the use of micro-threads to manage a register file cache.

Support: The University of Adelaide