Design Verification Projects

Hardware Verification Techniques for Complex High Performance Systems-on-a-chip

(Contact:  Dr. C.C. Lim, cclim@eleceng.adelaide.edu.au)

Verifying the correctness of modern integrated circuit designs is a critical success factor from both economic and technological perspectives. Rapid advances in semiconductor manufacturing technology are not matched by similar gains in hardware design verification methodology. This creates a widening verification gap that threatens the viability of future complex ICs. This project aims to address this issue by developing novel hardware verification techniques targeting complex high performance systems-on-a-chip. The research outcome will be a set of verification techniques and tools that directly benefit the advancement of future IC development, verification and manufacturing. The research is built on the verification flow SALVEM (software application level verification methodology). Conceptually, SALVEM uses embedded software applications to excite interactions across multiple software and hardware layers of the SoC architecture. Test generation and coverage are two main functions performed by SALVEM. Our application test cases are generated using small modular segments of common software SoC code, called snippets. Coverage makes use of control graphs and symbolic trajectory evaluation techniques.

Support: Australian Research Council, Freescale Semiconductor, Australian Postgraduate Awards

Testability Properties of Asynchronous Circuits

(Contact:  Mr. M.J. Liebelt, mike@eleceng.adelaide.edu.au)

Asynchronous digital circuits have several potential advantages over synchronous circuits and there is a great deal of current research on asynchronous design methods. If asynchronous methods are to be widely accepted it is necessary that comprehensive CAD tools be developed and that there be efficient test techniques for VLSI asynchronous circuits. There has been and is a lot of research on test methods and design for testability of synchronous circuits. Some of these techniques are applicable to asynchronous circuits, particularly to data path sections, but with most modern asynchronous design methods the control circuits have very different characteristics to synchronous control circuits. Novel approaches to testing asynchronous control circuits are often required. Fortunately, many asynchronous control circuits possess properties that make them somewhat self-checking. The existing body of results, however, is limited in scope, addressing only stuck-at faults and a useful, but limited range of synchronous circuits. In this project we are seeking to extend the scope of the existing self-checking results, to develop results for fault models which are more realistic than the stuck-at fault model and to establish design for testability guidelines and test strategies for VLSI asynchronous circuits.

Support: The University of Adelaide, Australian Research Council